1. Field of the Invention
The present invention relates to integrated circuit testing, and more particularly to a system and method for controlling temperatures of a chip during testing.
2. Description of the Related Art
As complementary metal oxide semiconductor (CMOS) technology scales, direct current (D.C.) leakage currents increase dramatically. This problem has risen to near crisis levels for high temperature burn-in testing used to accelerate processing faults in CMOS integrated circuits. Technology scaling has permitted multiple cores to exist on the same chip. Cores may be discrete energy sources and may be associated with parts of a chip (e.g., functional blocks), such as processors, parts thereof or other components, which generate heat. Device leakage at test temperatures in excess of 140° C. can dissipate leakage power in excess of 2000 Watts. This high power at voltages of 1 Volt results in excessive current draw.
These currents exceed the limits of current test equipment. Conventional methods for high temperature testing use a test oven or hot plate to heat the entire silicon chip, while a high stress voltage is applied to the chip under test (CUT). FIG. 1 shows a rendering of a heat map of a conventional multiprocessor chip under burn-in test while being heated by a thermal oven. In this example, a multiprocessor chip 10 includes two identical processor cores 12 and 14, and a shared SRAM cache 16. A uniform solid color indicates a uniform high heat map emanating from the chip under test operation. Diagonal shading indicates lower temperatures, and dotted shading indicates higher temperatures.
During conventional test operation, the entire chip 10 is heated to a high burn-in temperature, while test vectors are applied to the chip by an automated tester, to electrically stimulate a portion of the chip in an effort to accelerate defects.
FIG. 2 shows the leakage current dependence of a typical CMOS 130 nm process. As can be seen in FIG. 2, as the temperature is elevated to a typical burn-in condition of 140 degrees Celsius, the D.C. leakage current consumption of the devices can increase by up to 5–10 times the value at normal operating conditions. The D.C. leakage current consumption typically constitutes up to 30% of the normal power consumption of a high performance processor. A 100 Amp processor core could easily have 30 Amps of leakage at normal operating temperatures. At high temperatures, the total core current consumption could increase to 250 Amps. Two cores would consume 500 Amps, and at 1.6 Volts power supply, the chip would consume over 800 Watts without including the SRAM cache.
Existing methods of using voltage islands can be used to partition the CUT into voltage islands to allow testing of individual portions of the chip. This method can be used to limit the total amount of current needed to be delivered to the chip, by only powering up a portion of the chip while it is being heated up. This method has drawbacks because it forces a voltage island to exist in the chip, and can limit maximum frequency of the chip in normal operation by creating non-uniform voltage regions. It also can increase the total number of supply pins needed for the chip.
Previous attempts at localized heating have been disclosed, which employed stepped laser shining on the backside of a chip in a system designed to isolate faults in the design. These systems used a constant current power source and measured the local change in supply voltage (VDD) as a way to isolate increased power consumption. This system is not intended and not suitable for high speed manufacturing burn-in since it relies on a constant current supply instead of a more typical elevated constant voltage supply. It also has no built in apparatus to allow direct detection of on-chip temperature to control the location of the laser beam.